发明授权
US07979781B2 Method and system for performing Viterbi decoding using a reduced trellis memory
有权
使用减小网格存储器执行维特比解码的方法和系统
- 专利标题： Method and system for performing Viterbi decoding using a reduced trellis memory
- 专利标题（中）： 使用减小网格存储器执行维特比解码的方法和系统
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申请号： US11708195申请日： 2007-02-20
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公开(公告)号： US07979781B2公开(公告)日： 2011-07-12
- 发明人: Eran Pisek
- 申请人： Eran Pisek
- 申请人地址： KR Suwon-si
- 专利权人： Samsung Electronics Co., Ltd.
- 当前专利权人： Samsung Electronics Co., Ltd.
- 当前专利权人地址： KR Suwon-si
- 主分类号： H03M13/00
- IPC分类号： H03M13/00
摘要：
A method for performing Viterbi decoding using a reduced trellis memory is provided that includes dividing a block of data into a plurality of segments. A feed-forward process is performed on each of the segments to generate a trellis for each of the segments. A traceback process is performed on each of a plurality of overlapping segment pairs, each segment pair comprising a first segment and a second segment, to generate a traceback result for the first segment and a traceback result for the second segment. The traceback result for the second segment is discarded to generate a decoder output based on the traceback result for the first segment.
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