发明授权
- 专利标题: Multi-serial interface stacked-die memory architecture
- 专利标题(中): 多串行接口堆叠存储器架构
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申请号: US12261942申请日: 2008-10-30
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公开(公告)号: US07978721B2公开(公告)日: 2011-07-12
- 发明人: Joe M. Jeddeloh , Paul A. LaBerge
- 申请人: Joe M. Jeddeloh , Paul A. LaBerge
- 申请人地址: US ID Boise
- 专利权人: Micron Technology Inc.
- 当前专利权人: Micron Technology Inc.
- 当前专利权人地址: US ID Boise
- 代理机构: Schwegman, Lundberg & Woessner, P.A.
- 主分类号: H04L12/28
- IPC分类号: H04L12/28 ; H04J3/00 ; G06F13/00 ; G06F13/28 ; G11C11/00
摘要:
Systems and methods disclosed herein substantially concurrently transfer a plurality of streams of commands, addresses, and/or data across a corresponding plurality of serialized communication link interfaces (SCLIs) between one or more originating devices or destination devices such as a processor and a switch. At the switch, one or more commands, addresses, or data corresponding to each stream can be transferred to a corresponding destination memory vault controller (MVC) associated with a corresponding memory vault. The destination MVC can perform write operations, read operations, and/or memory vault housekeeping operations independently from concurrent operations associated with other MVCs coupled to a corresponding plurality of memory vaults.
公开/授权文献
- US20100005238A1 MULTI-SERIAL INTERFACE STACKED-DIE MEMORY ARCHITECTURE 公开/授权日:2010-01-07
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