A resolver interface includes separate anti-aliasing filters for sine and cosine signals. The separately filtered signals are then time share multiplexed to a single analog to digital (A/D) converter. Because all of the inputs are fed through the same A/D converter, any error, difference or shift caused by the A/D converter is shared across al of the inputs. A Field Programmable Gate Array (FPGA) and processor are used to digitally filter, demodulate and compute position.