发明授权
- 专利标题: Semiconductor device and manufacturing method for semiconductor device
- 专利标题(中): 半导体装置及半导体装置的制造方法
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申请号: US12491997申请日: 2009-06-25
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公开(公告)号: US07977739B2公开(公告)日: 2011-07-12
- 发明人: Tsuyoshi Kachi
- 申请人: Tsuyoshi Kachi
- 申请人地址: JP Kawasaki-shi
- 专利权人: Renesas Electronics Corporation
- 当前专利权人: Renesas Electronics Corporation
- 当前专利权人地址: JP Kawasaki-shi
- 代理机构: Miles & Stockbridge P.C.
- 优先权: JP2008-190971 20080724
- 主分类号: H01L29/72
- IPC分类号: H01L29/72
摘要:
Generally, a power MOSFET mainly includes an active region occupying most of an internal region (a region where a gate electrode made of polysilicon or the like is integrated), and a surrounding gate contact region (where the gate electrode made of polysilicon or the like is derived outside a source metal covered region to make contact with a gate metal) (see FIG. 65 in a comparative example). Since the gate electrode made of polysilicon or the like has a stepped portion existing between both regions, a focus margin may be reduced in a lithography step, including exposure or the like, for formation of a contact hole for a source or for a gate. The invention of the present application provides a semiconductor device having a trench gate type power MISFET with a gate electrode protruding from an upper surface of a semiconductor substrate, in which respective main upper surfaces of the gate electrode in an active region and a gate contact region are substantially at the same height.
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