发明授权
US07925867B2 Pre-decode checking for pre-decoded instructions that cross cache line boundaries
有权
预先解码检查跨越高速缓存线边界的预解码指令
- 专利标题: Pre-decode checking for pre-decoded instructions that cross cache line boundaries
- 专利标题(中): 预先解码检查跨越高速缓存线边界的预解码指令
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申请号: US12458512申请日: 2009-07-14
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公开(公告)号: US07925867B2公开(公告)日: 2011-04-12
- 发明人: Peter Richard Greenhalgh , Max Zardini , Allan John Skillman , Daniel Paul Schostak
- 申请人: Peter Richard Greenhalgh , Max Zardini , Allan John Skillman , Daniel Paul Schostak
- 申请人地址: GB Cambridge
- 专利权人: ARM Limited
- 当前专利权人: ARM Limited
- 当前专利权人地址: GB Cambridge
- 代理机构: Nixon & Vanderhye P.C.
- 主分类号: G06F9/30
- IPC分类号: G06F9/30
摘要:
A data processing and method are provided for pre-decoding instructions. The data processing apparatus has pre-decoding circuitry for receiving instructions fetched from a memory and for performing a pre-decoding operation to generate corresponding pre-decoded instructions, which are then stored in the cache for access by the processing circuitry. If a pre-decoded instruction crosses a cache line boundary, then checking circuitry in respect of selected types of pre-decoded instruction checks for consistency between the first portion of the pre-decoded instruction stored within a first cache line and a contiguous second portion of the pre-decoded instruction stored within a second cache line. If this consistency check is passed such that the two portions are self-consistent, then the pre-decoded instruction can be further decoded and issued. If the consistency check is failed, or the pre-decoded instruction is not of a type for which consistency checking is supported, then re-generation of the pre-decoded instruction is triggered.
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