发明授权
US07924619B2 Programming method to reduce word line to word line breakdown for NAND flash
有权
用于减少NAND闪存字线到字线的编程方法
- 专利标题: Programming method to reduce word line to word line breakdown for NAND flash
- 专利标题(中): 用于减少NAND闪存字线到字线的编程方法
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申请号: US12502537申请日: 2009-07-14
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公开(公告)号: US07924619B2公开(公告)日: 2011-04-12
- 发明人: Seiichi Aritome
- 申请人: Seiichi Aritome
- 申请人地址: US ID Boise
- 专利权人: Micron Technology, Inc.
- 当前专利权人: Micron Technology, Inc.
- 当前专利权人地址: US ID Boise
- 代理机构: Leffert Jay & Polglaze, P.A.
- 主分类号: G11C16/10
- IPC分类号: G11C16/10 ; G11C16/06 ; G11C16/12 ; G11C7/02 ; G11C8/08
摘要:
A NAND architecture non-volatile memory device and programming process programs the various cells of strings of non-volatile memory cells by the application of differing word line pass voltages (Vpass) to the unselected word lines adjacent to the selected word line and memory cell being programmed in order to reduce voltage differences between the word lines of the memory cell string or array during a programming cycle. This allows the word line to word line voltage differential to be reduced and thus decreases the likelihood of breakdown or punch through of the insulator materials placed between the adjacent word lines.
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