发明授权
US07921401B2 Stress analysis method, wiring structure design method, program, and semiconductor device production method
有权
应力分析方法,接线结构设计方法,程序和半导体器件的制造方法
- 专利标题: Stress analysis method, wiring structure design method, program, and semiconductor device production method
- 专利标题(中): 应力分析方法,接线结构设计方法,程序和半导体器件的制造方法
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申请号: US11703218申请日: 2007-02-07
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公开(公告)号: US07921401B2公开(公告)日: 2011-04-05
- 发明人: Sachiyo Ito , Masahiko Hasunuma , Hisashi Kaneko
- 申请人: Sachiyo Ito , Masahiko Hasunuma , Hisashi Kaneko
- 申请人地址: JP Tokyo
- 专利权人: Kabushiki Kaisha Toshiba
- 当前专利权人: Kabushiki Kaisha Toshiba
- 当前专利权人地址: JP Tokyo
- 代理机构: Finnegan, Henderson, Farabow, Garrett & Dunner, L.L.P.
- 优先权: JP2006-031694 20060208
- 主分类号: G06F17/50
- IPC分类号: G06F17/50 ; G06F11/22
摘要:
A stress analysis method is provided: including dividing, by using a division unit, an inside of a chip into a plurality of analysis areas, deriving, by using a composite property derivation unit, a composite property into which physical property values of a plurality of materials included in an analysis area are compounded, about each of the plurality of analysis areas on the basis of wiring structure data for each of the plurality of analysis areas, and creating, by using a stress analysis unit, a three-dimensional model of a finite element method which uses each analysis area as an element, to apply the composite property to each element, and to perform a stress analysis.
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