A clock and data recovery circuit includes a four-phase generation circuit that generates four-phase clock signals with phases thereof being equally spaced by 90 degrees, a first interpolator and a second interpolator, each of which receives two of the clocks with phases thereof separated to each other by 180 degrees, performs phase interpolation, and outputs a signal obtained by the interpolation and a signal with a phase reverse to a phase of the interpolated signal. A four-phase to eight-phase conversion circuit receives the four-phase clocks from the first and second interpolators, buffers the four-phase clock signals output from the first interpolator and the second interpolator and outputs the buffered four-phase clock signals without alteration, and generates four-phase clocks each obtained by interpolation of two of the clock signals with the mutually adjacent phases among the four-phase clock signals output from the first interpolator and the second interpolator.