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发明授权
US07847592B2 Buffer circuit of semiconductor memory apparatus 失效
半导体存储装置的缓冲电路

Buffer circuit of semiconductor memory apparatus
摘要：
A buffer circuit of a semiconductor memory apparatus includes a buffering section configured to increase or decrease a voltage level of an output node by comparing a voltage level of an input signal with a voltage level of a reference voltage. A voltage compensation section applies a voltage to the output node in proportion to a variation of the reference voltage when the level of the reference voltage is lower than a target level.
摘要（中）：

半导体存储装置的缓冲电路包括：缓冲部，被配置为通过将输入信号的电压电平与参考电压的电压电平进行比较来增大或减小输出节点的电压电平。 当参考电压的电平低于目标电平时，电压补偿部分与输出节点成比例地与参考电压的变化成比例。

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