Invention Grant
- Patent Title: Multilayer build-up wiring board including a chip mount region
- Patent Title (中): 包括芯片安装区域的多层积层线路板
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Application No.: US12406009Application Date: 2009-03-17
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Publication No.: US07847318B2Publication Date: 2010-12-07
- Inventor: Naohiro Hirose , Honjin En
- Applicant: Naohiro Hirose , Honjin En
- Applicant Address: JP Ogaki-shi
- Assignee: IBIDEN Co., Ltd.
- Current Assignee: IBIDEN Co., Ltd.
- Current Assignee Address: JP Ogaki-shi
- Agency: Oblon, Spivak, McClelland, Maier & Neustadt, L.L.P.
- Priority: JP10-283437 19980917; JP10-324535 19981028; JP10-362961 19981221; JP11-000315 19990105
- Main IPC: H01L29/40
- IPC: H01L29/40 ; H05K7/20

Abstract:
Mesh holes 35a and 59a of upper solid layers 35 and upper solid layers 59 are formed to overlie on one another, so that the insulating properties of interlayer resin insulating layers 50 are not lowered. Here, the diameter of each mesh hole is preferably 75 to 300 μm. The reason is as follows. If the diameter of the mesh hole is less than 75 μm, it is difficult to overlay the upper and lower mesh holes on one another. If the diameter exceeds 300 μm, the insulating properties of the interlayer resin insulating layers deteriorate. In addition, the distance between the mesh holes is preferably 100 to 2000 μm. The reason is as follows. If the distance is less than 100 μm, the solid layer cannot function. If the distance exceeds 2000 μm, the deterioration of the insulating properties of the interlayer resin insulating film occurs.
Public/Granted literature
- US20090173523A1 MULTILAYER BUILD-UP WIRING BOARD Public/Granted day:2009-07-09
Information query
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