A switching chip for performing switching and other functions on packets transmitted through the switching chip. The switching chip includes a memory management unit that identifies a class of service to which each packet belongs, wherein upon processing the packet. The memory management unit transmits the packet to a CPU through a CPU processing module. The switching chip also includes a CPU processing module that includes a class of service bitmap that is associated with a plurality of channels. Each of the plurality of channels is further associated with at least one class of service, includes a per channel bit and is assigned a predefined priority level. Upon receiving packets from the memory management unit, the CPU processing module is configured to sort the packets according to the class of service to which the packet belongs and store each packet in an associated one of the plurality of channels. The CPU processing module is also configured to use the per channel bit to determine how to process packets in each for the plurality of channels for which there is no available CPU buffer. When there is no available CPU buffer for one of the plurality of channels, the CPU processing module is configured to set an appropriate bit in the class of service bitmap and transmits the class of service bitmap to the memory management unit.