Invention Grant
US07790540B2 Structure and method to use low k stress liner to reduce parasitic capacitance
失效
使用低k应力衬垫降低寄生电容的结构和方法
- Patent Title: Structure and method to use low k stress liner to reduce parasitic capacitance
- Patent Title (中): 使用低k应力衬垫降低寄生电容的结构和方法
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Application No.: US11467186Application Date: 2006-08-25
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Publication No.: US07790540B2Publication Date: 2010-09-07
- Inventor: Haining Yang , Wai-Kin Li
- Applicant: Haining Yang , Wai-Kin Li
- Applicant Address: US NY Armonk
- Assignee: International Business Machines Corporation
- Current Assignee: International Business Machines Corporation
- Current Assignee Address: US NY Armonk
- Agency: Scully, Scott, Murphy & Presser, P.C.
- Agent Katherine S. Brown, Esq.
- Main IPC: H01L21/8238
- IPC: H01L21/8238
Abstract:
A low k stress liner, which replaces conventional stress liners in CMOS devices, is provided. In one embodiment, a compressive, low k stress liner is provided which can improve the hole mobility in pFET devices. UV exposure of this compressive, low k material results in changing the polarity of the low k stress liner from compressive to tensile. The use of such a tensile, low k stress liner improves electron mobility in nFET devices.
Public/Granted literature
- US20080048271A1 STRUCTURE AND METHOD TO USE LOW k STRESS LINER TO REDUCE PARASITIC CAPACITANCE Public/Granted day:2008-02-28
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