发明授权
US07721167B1 Apparatus and method for testing and debugging an integrated circuit
有权
用于集成电路测试和调试的装置和方法
- 专利标题: Apparatus and method for testing and debugging an integrated circuit
- 专利标题(中): 用于集成电路测试和调试的装置和方法
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申请号: US12154896申请日: 2008-05-28
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公开(公告)号: US07721167B1公开(公告)日: 2010-05-18
- 发明人: Saeed Azimi , Son Ho , Daniel Smathers
- 申请人: Saeed Azimi , Son Ho , Daniel Smathers
- 申请人地址: BE Hamilton
- 专利权人: Marvell International Ltd.
- 当前专利权人: Marvell International Ltd.
- 当前专利权人地址: BE Hamilton
- 主分类号: G01R31/28
- IPC分类号: G01R31/28
摘要:
A system for receiving Joint Task Action Group (JTAG) data bits from a device under test includes a deserializer that receives serial messages from the device under test and forms data frames based on the serial messages. A frame sync module communicates with the deserializer and forms JTAG data bits based on the data frames. N virtual JTAG test access ports (VTAPs), each having an input and an output. The N VTAPs are connected in a daisy chain and the input of a first VTAP receives the JTAG data bits from the frame sync module.
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