发明授权
US07652513B2 Slave latch controlled retention flop with lower leakage and higher performance
有权
从锁存控制保持触发器具有较低的泄漏和更高的性能
- 专利标题: Slave latch controlled retention flop with lower leakage and higher performance
- 专利标题(中): 从锁存控制保持触发器具有较低的泄漏和更高的性能
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申请号: US11895853申请日: 2007-08-27
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公开(公告)号: US07652513B2公开(公告)日: 2010-01-26
- 发明人: Bindu Prabhakar Rao , Sumanth Katte Gururajarao , Dharin N. Shah
- 申请人: Bindu Prabhakar Rao , Sumanth Katte Gururajarao , Dharin N. Shah
- 申请人地址: US TX Dallas
- 专利权人: Texas Instruments Incorporated
- 当前专利权人: Texas Instruments Incorporated
- 当前专利权人地址: US TX Dallas
- 代理商 Dawn V. Stephens; Wade James Brady, III; Frederick J. Telecky, Jr.
- 主分类号: H03K3/356
- IPC分类号: H03K3/356
摘要:
In a method and apparatus for data retention, a first latch latches a data input and a second latch that is coupled to the first latch retains the data input while the first latch is inoperative in a standby power mode. The second latch includes a second latch inverter having an inverter input and an inverter output. A switching circuit, which may be implemented as a tristate inverter, is coupled to the inverter output, the inverter input, and a retention signal. The switching circuit is operable in the standby power mode to assert a logic state at the inverter input responsive to the retention signal. The logic state is in accordance with the data input retained in the standby power mode. A standby power source is operable to provide power in the standby power mode to the second latch inverter, the switching circuit and the retention input.
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