Various techniques are described to test memory arrays of a programmable logic device (PLD). In one example, a PLD includes a first memory array. The PLD also includes a plurality of sense amplifiers adapted to read a plurality of data values stored by the first memory array and provide a plurality of data signals corresponding to the data values. The PLD further includes a test circuit adapted to test the first memory array. The test circuit is coupled with the sense amplifiers and adapted to compare the data signals with a test signal to provide a pass/fail signal. In addition, the PLD includes a second memory array. The PLD also includes a data shift register adapted to test the second memory array.