A gate wire including a gate line and a gate electrode is formed on a substrate and a gate insulating layer is formed on the substrate. A semiconductor pattern and an etching assistant pattern are formed on the gate insulating layer and a source/drain conductor pattern and an etching assistant layer are formed on the semiconductor pattern and the etching assistant pattern. A data wire including a data line and source and drain electrodes separated from each other is formed by removing the etching assistant layer and partly removing the source/drain conductor pattern. A pixel electrode connected to the drain electrodes is formed.