A digital camera includes a signal processing circuit. The signal processing circuit makes signal processing on the camera data read from a camera data area of an SDRAM to produce YUV data for record. A thin-out circuit makes a thin-out processing on the recording YUV data to produce YUV data for display. The display YUV data and the recording YUV data thus produced are written respectively to a display data area and a recording data area of the SDRAM and thereafter processed for display on a display and record to a flash memory. The access speed to SDRAM is 48 MHz and the processing speed of the signal processing circuit and thin-out circuit is 12 MHz. Consequently, the YUV data for display and YUV data for record is written concurrently with reading out of the camera data.