发明授权
- 专利标题： Fabrication method of semiconductor integrated circuit device and mask fabrication method
- 专利标题（中）： 半导体集成电路器件的制造方法和掩模制造方法
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申请号： US10762548申请日： 2004-01-23
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公开(公告)号： US07252910B2公开(公告)日： 2007-08-07
- 发明人: Norio Hasegawa , Katsuya Hayano , Shinji Kubo , Yasuhiro Koizumi , Yasushi Kawai
- 申请人： Norio Hasegawa , Katsuya Hayano , Shinji Kubo , Yasuhiro Koizumi , Yasushi Kawai
- 申请人地址： JP Tokyo JP Tokyo
- 专利权人： Renesas Technology Corp.,Dai Nippon Printing Co., Ltd.
- 当前专利权人： Renesas Technology Corp.,Dai Nippon Printing Co., Ltd.
- 当前专利权人地址： JP Tokyo JP Tokyo
- 代理机构： Antonelli, Terry, Stout & Kraus, LLP.
- 优先权： JPP2003-014838 20030123
- 主分类号： G03F1/00
- IPC分类号： G03F1/00
摘要：
A mask fabrication time is shortened. By patterning an electron-sensitive resist film coated on a main surface of a mask substrate, a pellicle is mounted on the main surface of the mask substrate immediately after a resist pattern made from an electron beam sensitive resist film and having light-shielding characteristics with respect to exposure light is formed. Subsequently, by irradiating a laser beam to defect made from the electron beam sensitive resist film with the pellicle being mounted on the mask substrate, the defect is removed. Since the defect can be removed without removing the pellicle, the mask fabrication time can be shortened.
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