Methods of forming a double metal salicide layer and methods of fabricating semiconductor devices incorporating the same

Invention Grant

US07238612B2 Methods of forming a double metal salicide layer and methods of fabricating semiconductor devices incorporating the same 有权

Title translation: 形成双金属硅化物层的方法及其制造的半导体器件的制造方法

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Patent Title: Methods of forming a double metal salicide layer and methods of fabricating semiconductor devices incorporating the same
Patent Title (中): 形成双金属硅化物层的方法及其制造的半导体器件的制造方法
Application No.: US11044884

Application Date: 2005-01-27
Publication No.: US07238612B2

Publication Date: 2007-07-03
Inventor: Jong-ho Yun , Gil-heyun Choi , Seong-hwee Cheong , Sug-woo Jung , Hyun-su Kim , Woong-hee Sohn
Applicant: Jong-ho Yun , Gil-heyun Choi , Seong-hwee Cheong , Sug-woo Jung , Hyun-su Kim , Woong-hee Sohn
Applicant Address: KR Gyeonggi-do
Assignee: Samsung Electronics Co., Ltd.
Current Assignee: Samsung Electronics Co., Ltd.
Current Assignee Address: KR Gyeonggi-do
Agency: Myers Bigel Sibley & Sajovec, PA
Priority: KR10-2004-0014958 20040305
Main IPC: H01L21/4763
IPC: H01L21/4763

Methods of forming a double metal salicide layer and methods of fabricating semiconductor devices incorporating the same

Abstract:

A metal salicide layer is formed by sequentially depositing a physical vapor deposition (PVD) metal layer and a chemical vapor deposition (CVD) metal layer on a semiconductor device having an exposed silicon surface so as to form a double metal layer. The semiconductor device is annealed to react the double metal layer with the silicon surface. At least a portion of the double layer that has not reacted with the silicon surface is stripped. The semiconductor device is annealed after stripping at least the portion of the double metal layer.

Abstract(Chinese):

通过在具有暴露的硅表面的半导体器件上依次沉积物理气相沉积（PVD）金属层和化学气相沉积（CVD）金属层以形成双金属层而形成金属硅化物层。将半导体器件退火以使双金属层与硅表面反应。剥离未与硅表面反应的双层的至少一部分。半导体器件在剥离至少双重金属层的部分之后进行退火。

Public/Granted literature

US20050196945A1 Methods of forming a double metal salicide layer and methods of fabricating semiconductor devices incorporating the same Public/Granted day:2005-09-08

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Espacenet

IPC分类:

H	电学
H01	基本电气元件
H01L	半导体器件；其他类目中不包括的电固体器件（使用半导体器件的测量入G01；一般电阻器入H01C；磁体、电感器、变压器入H01F；一般电容器入H01G；电解型器件入H01G9/00；电池组、蓄电池入H01M；波导管、谐振器或波导型线路入H01P；线路连接器、汇流器入H01R；受激发射器件入H01S；机电谐振器入H03H；扬声器、送话器、留声机拾音器或类似的声机电传感器入H04R；一般电光源入H05B；印刷电路、混合电路、电设备的外壳或结构零部件、电气元件的组件的制造入H05K；在具有特殊应用的电路中使用的半导体器件见应用相关的小类）
H01L21/00	专门适用于制造或处理半导体或固体器件或其部件的方法或设备
H01L21/02	.半导体器件或其部件的制造或处理
H01L21/04	..至少具有一个跃变势垒或表面势垒的器件，例如PN结、耗尽层、载体集结层
H01L21/34	...具有H01L21/06，H01L21/16及H01L21/18各组不包含的或有或无杂质，例如掺杂材料的半导体的器件
H01L21/46	....用H01L21/36至H01L21/428各组不包含的方法或设备处理半导体材料的（在半导体材料上制作电极的入H01L21/44）
H01L21/461	.....改变半导体材料的表面物理特性或形状的，例如腐蚀、抛光、切割
H01L21/4763	......非绝缘层的沉积，例如绝缘层上的导电层、电阻层；这些层的后处理（电极的制造入H01L21/28）