Invention Grant
- Patent Title: Differential output circuit with reduced differential output variation
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Application No.: US11103515Application Date: 2005-04-12
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Publication No.: US07227410B2Publication Date: 2007-06-05
- Inventor: Hideo Nagano , Keisuke Aoyagi , Masao Suzuki
- Applicant: Hideo Nagano , Keisuke Aoyagi , Masao Suzuki
- Applicant Address: JP Tokyo
- Assignee: Renesas Technology Corp.
- Current Assignee: Renesas Technology Corp.
- Current Assignee Address: JP Tokyo
- Agency: McDermott Will & Emery LLP
- Priority: JP2004-119303 20040414
- Main IPC: H03F3/217
- IPC: H03F3/217

Abstract:
In a differential output circuit, a second amplifier has a positive terminal connected to a second fixed potential and a negative terminal to a fifth switch at a first terminal. First and second switches are connected at a point connected to the fifth switch at a second terminal and to a first load. Third and fourth switches are connected at a point connected to the fifth switch at a third terminal and to a second load. The second terminal is connected to the first terminal when the second and third switches turn on. The third terminal is connected to the first terminal when the first and fourth switches turn on.
Public/Granted literature
- US20050231282A1 Differential output circuit with reduced differential output variation Public/Granted day:2005-10-20
Information query
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