A technique for testing an electronics assembly for a power short circuit is provided. The technique includes pre-characterizing power off resistance of an electronic component(s) of a first packaging level from at least one power boundary of the electronic component(s). The characterizing of the power off resistance occurs prior to placement of the electronic component(s) into an electronics assembly of a higher packaging level. The technique further includes determining actual power off resistance of the electronics component(s) after placement thereof into the electronics assembly, with the actual power off resistance being determined from the at least one power boundary. Thereafter, the actual power off resistance of the electronic component(s) in the electronics assembly is compared with the pre-characterized power off resistance of the at least one electronic component(s), and a determination is made therefrom whether a power short circuit exists within the electronics assembly.