Invention Grant
- Patent Title: Integrated circuit with bonding layer over active circuitry
- Patent Title (中): 在有源电路上具有接合层的集成电路
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Application No.: US10191453Application Date: 2002-07-10
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Publication No.: US06683380B2Publication Date: 2004-01-27
- Inventor: Taylor R. Efland , Donald C. Abbott , Walter Bucksch , Marco Corsi , Chi-Cheong Shen , John P. Erdeljac , Louis N. Hutter , Quang X. Mai , Konrad Wagensohner , Charles E. Williams , Milton L. Buschbom
- Applicant: Taylor R. Efland , Donald C. Abbott , Walter Bucksch , Marco Corsi , Chi-Cheong Shen , John P. Erdeljac , Louis N. Hutter , Quang X. Mai , Konrad Wagensohner , Charles E. Williams , Milton L. Buschbom
- Main IPC: H01L2348
- IPC: H01L2348

Abstract:
An integrated circuit device (10) with a bonding surface (12) directly over its active circuitry, and a method of making such integrated circuits (FIGS. 2A-2E). To make the bonding surface (12), a wafer (20) is provided with vias (24) to its metallization layer (21) and then coated with a seed metal layer (25). A plating pattern (26) is formed on the wafer (20), exposing portions of the seed metal layer (25) and blocking the rest of the seed metal layer (25). These exposed portions are plated with successive metal layers (27, 28, 29), thereby forming a bonding surface (12) having a number of layered stacks (200) that fill the vias (24). The plating pattern and the nonplated portions of the seed metal layer (25) are then removed.
Public/Granted literature
- US20030036256A1 Integrated circuit with bonding layer over active circuitry Public/Granted day:2003-02-20
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