A split-gate flash memory includes a first gate insulating layer formed on a semiconductor substrate; a floating gate formed on the first gate insulating layer; a first spacer surrounding the floating gate and a side wall; a first junction region formed on a predetermined portion of the semiconductor substrate between two adjacent floating gates and having an opposite conductivity to that of the semiconductor substrate; a first conductive line formed on the first junction region between two adjacent first spacers; a second gate insulating layer formed on both a predetermined portion of the semiconductor substrate and the side wall of the first spacer; a word line formed on the second gate insulating layer, and having a vertical side wall and a uniform width; a second spacer formed on the vertical side wall of the word line; a second junction region formed on a portion of the semiconductor substrate adjacent the second spacer and having the same conductivity as the first junction region; an interlayer insulator formed over the whole surface of the semiconductor and having a contact hole, the contact hole formed on a portion of the second junction region; and a second conductive line formed on the interlayer insulator and contacting the second junction region through the contact hole.