Plurality of latch circuits 21, 23 are provided for storing therein written data (D0˜D7), and there is also a register (multiplexed latch circuit) having data bus drivers for storing the data in a specified latch circuit of the plurality of latch circuits correlated to security levels (SECU1 and SECU1 signals) for writing/reading the data to/from the latch circuits and connecting only the latch circuit correlated to a prespecified security level (SECU2 signal) of the security levels to a specified circuit (internal circuit) using the data, and outputting, when there is a request (RDS signal) to read data (D0˜D7), the data stored in a storage circuit correlated to the security level of the plurality of latch circuits.