发明授权
US06262612B1 Using storage elements with multiple delay values to reduce supply current spikes in digital circuits
有权
使用具有多个延迟值的存储元件来减少数字电路中的电源电流尖峰
- 专利标题： Using storage elements with multiple delay values to reduce supply current spikes in digital circuits
- 专利标题（中）： 使用具有多个延迟值的存储元件来减少数字电路中的电源电流尖峰
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申请号： US09543401申请日： 2000-04-05
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公开(公告)号： US06262612B1公开(公告)日： 2001-07-17
- 发明人: Lars Svensson , Alf Jörgen Peter Larsson
- 申请人： Lars Svensson , Alf Jörgen Peter Larsson
- 主分类号： H03L700
- IPC分类号： H03L700
摘要：
Commonly clocked digital storage elements are provided with mutually different clock-to-output delays in order to timewise stagger their respective switching current spikes from one another, thereby “smearing” the aggregate current spike over time.
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