An improved voltage level detecting circuit that provides stable voltage detection. The voltage level detecting circuit senses a level of a voltage to be detected only when two clock signals are at a low level after ORing the signals. After detecting the voltage level, the circuit reduces power consumption by preventing a current path between the voltage and ground. Consistent operation of the voltage level detecting circuit is achieved despite fluctuation of the voltage level to be detected caused by noise through detecting the level of the voltage only when a specific clock signal is enabled.