A vertical PNP transistor (11) and method for making it includes forming an N- region (19) in a P substrate (12), and forming an N+ region (26) in the substrate (12) laterally surrounding and partially extending into the N- region (19). A P region (30) is formed above the N- region (19), bounded laterally by the N+ region (26) to be horizontally and vertically isolated from the substrate (12) by the N- and N+ regions (19 and 26). A layer of semiconductor material (32) is formed overall, and an N well (35) and a surrounding P well (36) are formed, each extending to the P region (30). An isolating N+ well (38) is formed surrounding the P well (36), extending to the buried N+ region (26). A P emitter region (40) and an N base contact region (41) are formed at a surface of the N well (35), and a P collector contact region (44) is formed at a surface of the P well (36). Preferably, a CMOS structure (10) may be constructed elsewhere on the substrate concurrently with at least some of the steps for making the isolated vertical PNP transistor (11). For example, in one embodiment, the step of forming a P emitter region (40), an N base contact region (41), and a P collector contact region (44) are performed as a part of the simultaneous formation of source and drain regions (47 and 48) of the CMOS structure (10) elsewhere on the substrate (12). In another embodiment, the step of forming an N base contact (54) and a P collector contact (53) are performed as a part of a simultaneous formation of source and drain regions of a CMOS structure elsewhere on the substrate. In this embodiment, a separate deeper a P emitter region (52) is formed in the N well (19) to increase the emitter X.sub.J.