A fast floating-point multiplication and accumulation unit (fmac) is described. The described fmac uses significantly less hardware, thereby yielding a fast and an inexpensive fmac. This fmac uses an m-bit carry propagation adder instead of a 3 m-bit carry propagation adder and a 2 m-bit normalizer instead of a 3 m-bit normalizer. The normalizer relies on a leading one detection, as opposed to leading one/zero prediction used in known fmac's. Even when the product of the multiplication is opposite in sign to the number added to the product, the fmac, disclosed here, only uses an m-bit adder and a 2 m-bit normalizer.