发明授权
US5619054A CMOS transistor and isolated back gate electrodes on an SOI substrate
失效
CMOS晶体管和SOI衬底上的隔离背栅电极
- 专利标题: CMOS transistor and isolated back gate electrodes on an SOI substrate
- 专利标题(中): CMOS晶体管和SOI衬底上的隔离背栅电极
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申请号: US468308申请日: 1995-06-06
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公开(公告)号: US5619054A公开(公告)日: 1997-04-08
- 发明人: Makoto Hashimoto
- 申请人: Makoto Hashimoto
- 申请人地址: JPX
- 专利权人: Sony Corporation
- 当前专利权人: Sony Corporation
- 当前专利权人地址: JPX
- 优先权: JPX6-156669 19940614
- 主分类号: H01L27/092
- IPC分类号: H01L27/092 ; H01L21/02 ; H01L21/336 ; H01L21/8238 ; H01L21/84 ; H01L27/08 ; H01L27/12 ; H01L29/78 ; H01L29/786 ; H01L27/01
摘要:
The present invention is intended to provide, in MOS transistors used as a bonding layer for silicon regions of an SOI substrate, an nMOS transistor on a silicon region of an SOI substrate which uses a polycrystalline silicon layer as a layer to be bonded with the silicon substrate and a pMOS transistor on another silicon region of the SOI substrate and electrically isolated back gate electrodes through a back gate insulation film on the silicon region side between the silicon regions and a polycrystalline silicon layer. A leak current is reduced and a malfunction of the transistors is eliminated by providing pickup electrodes for the back gate electrodes.
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