A compensating transistor (Q5) is connected in series with the collector of a main transistor (Q3), and a level shifted replica (Vin+V1) of an input signal (Vin) is applied to the base of the compensating transistor (Q5) to maintain a constant voltage difference between the base and collector of the main transistor (Q3) and compensate for base width modulation .DELTA.Vce. A voltage-controlled current source (S1) is responsive to the input signal (Vin) and applies a compensating current .DELTA.Iload which is equal and opposite to the load current variation caused by a change (.DELTA.Vin) in the input voltage (Vin) to the emitter of the main transistor (Q3) to compensate for load current modulation .DELTA.Vbe. Alternatively, the compensating current can be applied to the junction of the base of the main transistor (Q3) and the emitter of pre-distortion transistor (Q4) which has a base connected to receive the input signal (Vin). Another compensating transistor (Q12) applies a current (.DELTA.Ib) which is equal and opposite to a non-linear base current variation to the emitter or collector of the main transistor (Q3) to compensate for current gain modulation .DELTA.Ib. The modulation compensation arrangements are applicable to common-collector, common-base and common emitter amplifiers in single-ended and differential configurations, and to substantially all bipolar and field-effect transistor technologies.