发明授权
- 专利标题： Pipelined buffer for analog signal and power supply
- 专利标题（中）： 用于模拟信号和电源的流水线缓冲器
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申请号： US854800申请日： 1992-03-23
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公开(公告)号： US5280200A公开(公告)日： 1994-01-18
- 发明人: Min M. Tarng
- 申请人： Min M. Tarng
- 专利权人： Tarng Min M
- 当前专利权人： Tarng Min M
- 主分类号： H01L27/07
- IPC分类号： H01L27/07 ; H01L27/11 ; H01L27/115 ; H03K19/086
摘要：
The analog dynamic superbuffer comprises the level shift stage, voltage clamping stage and the dynamic buffer stage. The clamping circuit enables the output buffer having the dynamic driving capability to drive a very large output load with very little static DC bias power consumption.The TTL power supply is constituted of the stages of TTL power level shift and the analog superbuffer. The huge impact of the power source load is completely blocked by the analog superbuffer.
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