Invention Grant
US4523295A Power loss compensation for programmable memory control system 失效
可编程存储器控制系统的功率损耗补偿

Power loss compensation for programmable memory control system
Abstract:
An arrangement for storing user programmed system timing information in a microprogrammable system in the event of a power outage. The system includes a static random access memory (RAM) for periodically storing microprocessor-generated timing information and an electrically erasable programmable ROM (EEPROM) which is coupled to the static RAM for the temporary storage of this information in the event of a power outage. Also provided in the system is a power down sensor responsive to an AC-coupled power supply for detecting power loss to the system. When the input voltage drops below a predetermined value, the contents of the static RAM are automatically transferred to the nonvolatile EEPROM. When system input power is restored, the stored contents of the nonvolatile EEPROM are automatically retransferred back to the static RAM for use by the microprocessor permitting the resumption of system operation as previously programmed on a time-shifted basis where the time shift equals the duration of the power outage. The system is particularly adapted for use with a user-programmed device, such as a television receiver or a video cassette recorder, in an environment where power outages of very short duration randomly occur. The present invention permits such a system to resume programmed system operation following resumption of power to the system without employing the combination of a battery, an oscillator, a CMOS RAM and appropriate recharging circuitry, as generally utilized in such systems.
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