Internal control and subroutine logic transfers data between a keyboard input, a random access memory, and a plurality of flipflop registers to perform arithmetic operations and transfers the results of these operations to a cathode ray tube output display. The flip-flop registers include a program register comprising a set of primary flip-flops for designating a subroutine to be performed and a set of secondary flip-flops for sequentially designating a group of one or more instructions to be executed in each state of the designated subroutine. The primary and secondary flip-flops are controlled by multiple feedback paths. Power switching is employed in the internal control and subroutine logic so that the subroutines and instructions are supplied with power only when they are to be executed. The flipflop registers also include a memory access register for receiving information read from and to be written into the random access memory. When a random access memory cycle is required, it is automatically interposed between the otherwise regularly recurring logic cycles by the internal control and subroutine logic. Separate logic circuits are provided for enabling the state of the secondary flip-flops to be directly transferred to the memory access register and vice versa so that encoded transfer vectors may be stored in the random access memory and subsequently decoded by the internal control and subroutine logic to permit unrestricted subroutine returns. In the keyboard input, two power supply returns are employed to define one bit of the keyboard encoder. The random access memory is partitioned into one portion addressed by a single bit in an address register and into another, larger portion addressed by the remaining bits in the address register. Each flip-flop of the machine is a J-K flip-flop provided with an adjustable threshold for noise immunity and with a high internal gain on the J-K inputs. In the cathode ray tube output display a recurring pattern generated by integration in only two directions is selectively blanked to display the results of the operations performed by the calculator. A tester may be connected to the machine for allowing all subroutines to be operated in a single step mode. The tester is provided with switches for initializing any internal state of the machine or stopping normal execution under any prescribed conditions and with apparatus for accessing the random access memory.