Invention Application
- Patent Title: SEMICONDUCTOR DEVICE AND METHOD
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Application No.: US18789349Application Date: 2024-07-30
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Publication No.: US20240395905A1Publication Date: 2024-11-28
- Inventor: Shahaji B. More , Shih-Chieh Chang
- Applicant: Taiwan Semiconductor Manufacturing Co, Ltd.
- Applicant Address: TW Hsinchu
- Assignee: Taiwan Semiconductor Manufacturing Co, Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Co, Ltd.
- Current Assignee Address: TW Hsinchu
- Main IPC: H01L29/66
- IPC: H01L29/66 ; H01L21/02 ; H01L21/04 ; H01L21/8234 ; H01L29/06 ; H01L29/417 ; H01L29/78

Abstract:
Methods are disclosed for forming a multi-layer structure including highly controlled diffusion interfaces between alternating layers of different semiconductor materials. According to embodiments, during a deposition of semiconductor layers, the process is controlled to remain at low temperatures such that an inter-diffusion rate between the materials of the deposited layers is managed to provide diffusion interfaces with abrupt Si/SiGe interfaces. The highly controlled interfaces and first and second layers provide a multi-layer structure with improved etching selectivity. In an embodiment, a gate all-around (GAA) transistor is formed with horizontal nanowires (NWs) from the multi-layer structure with improved etching selectivity. In embodiments, horizontal NWs of a GAA transistor may be formed with substantially the same size diameters and silicon germanium (SiGe) NWs may be formed with “all-in-one” silicon (Si) caps.
Information query
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