An integrated circuit includes a sequential logic circuit and a circuit configured to change operation as a function of state output signals provided by state flip-flops of the sequential logic circuit. With a test mode signal asserted, a test circuit writes and reads the content of the state flip-flops in order to test the operation of the sequential logic circuit. A processing system includes at least one storage circuit interposed between the circuit and a respective state output signal. Each storage circuit receives the respective state output signal and provides a modified state signal to the circuit. When the test mode signal is de-asserted, the storage circuit provides the received state output signal in a transparent manner to the circuit and stores the received state output signal to a storage element. When the test mode signal is asserted, the storage circuit provides the stored state output signal to the circuit.