Invention Publication
- Patent Title: DETERMINING LATENCY AT A PHYSICAL LAYER
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Application No.: US18430152Application Date: 2024-02-01
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Publication No.: US20240267311A1Publication Date: 2024-08-08
- Inventor: Dixon Chen , Jiachi Yu , Kevin Yang , Venkatraman Iyer , Nihat Kaya
- Applicant: Microchip Technology Incorporated
- Applicant Address: US AZ Chandler
- Assignee: Microchip Technology Incorporated
- Current Assignee: Microchip Technology Incorporated
- Current Assignee Address: US AZ Chandler
- Priority: CN 2310121644.5 2023.02.02
- Main IPC: H04L43/0852
- IPC: H04L43/0852 ; H04L69/323
Abstract:
One or more examples relate, generally, to a method that includes: recording a value representing a time duration for a frame moving toward a cable or MAC to travel between a predetermined reference plane of a PHY-MAC interface to a predetermined reference plane of a PHY-able interface; and asserting an indication that the recorded value is available to be read from a PHY.
Information query
