Invention Publication
- Patent Title: STRUCTURE AND FORMATION METHOD OF PACKAGE WITH INTEGRATED CHIPS
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Application No.: US18163416Application Date: 2023-02-02
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Publication No.: US20240266340A1Publication Date: 2024-08-08
- Inventor: Chih-Chao CHOU , Yi-Hsun CHIU , Shang-Wen CHANG , Ching-Wei TSAI , Chih-Hao WANG
- Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicant Address: TW Hsinchu
- Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee Address: TW Hsinchu
- Main IPC: H01L25/00
- IPC: H01L25/00 ; H01L23/00 ; H01L23/522 ; H01L23/528 ; H01L25/065

Abstract:
A package structure and a formation method are provided. The method includes disposing a first chip structure over a carrier substrate. The first chip structure has a front-side interconnection structure facing the carrier substrate. The method also includes forming a back-side interconnection structure over the first chip structure. The first chip structure has a device portion between the back-side interconnection structure and the front-side interconnection structure. The back-side interconnection structure has stacked conductive vias. The method further includes bonding a second chip structure to the first chip structure using dielectric-to-dielectric bonding and metal-to-metal bonding.
Information query
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