Invention Publication
- Patent Title: WORD LINE CHARGE INTEGRATION
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Application No.: US18528451Application Date: 2023-12-04
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Publication No.: US20240212736A1Publication Date: 2024-06-27
- Inventor: Ferdinando Bedeschi , Umberto Di Vincenzo
- Applicant: Micron Technology, Inc.
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Main IPC: G11C11/22
- IPC: G11C11/22 ; G11C11/408 ; G11C11/4091

Abstract:
Methods, systems, and devices for word line charge integration are described. In some examples, a memory device may include a plurality of memory cells that are coupled with a word line and respective digit lines. During a read operation, the word line may be activated (e.g., driven to a voltage) and a subset of the respective digit lines may be activated (e.g., driven to a voltage) to begin integrating charges of each of the memory cells. Before each digit line is activated, the word line may be deactivated and the remaining digit lines may be activated (e.g., driven to a voltage) to begin integrating charges of the remaining memory cells that are coupled with the word line. After each of the digit lines are selected, respective sense components may be activated to sense the charges associated with the memory cells.
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