Invention Publication
- Patent Title: STACKED SEMICONDUCTOR PACKAGE
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Application No.: US18533800Application Date: 2023-12-08
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Publication No.: US20240194648A1Publication Date: 2024-06-13
- Inventor: Dawoon Jung , Seungduk Baek , Donghun Lee
- Applicant: Samsung Electronics Co., Ltd.
- Applicant Address: KR Suwon-si
- Assignee: Samsung Electronics Co., Ltd.
- Current Assignee: Samsung Electronics Co., Ltd.
- Current Assignee Address: KR Suwon-si
- Priority: KR 20220170256 2022.12.08
- Main IPC: H01L25/065
- IPC: H01L25/065 ; H01L23/00 ; H10B80/00

Abstract:
A semiconductor package includes a base structure and a plurality of semiconductor chips disposed on the base structure. Each of the plurality of semiconductor chips has a chip region. The plurality of semiconductor chips are stacked in a vertical direction such that chip regions at least partially overlap each other. In the stack of the plurality of semiconductor chips, each of the plurality of semiconductor chips has a first width in a first direction and a second width in a second direction. The plurality of semiconductor chips include a first semiconductor chip and a second semiconductor chip, having scribe regions on opposite sides of each of the chip regions. A first width of the first semiconductor chip is greater than a first width of the second semiconductor chip.
Information query
IPC分类: