Invention Publication
- Patent Title: Methods of Integrated Chip of Ultra-Fine Pitch Bonding and Resulting Structures
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Application No.: US18151714Application Date: 2023-01-09
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Publication No.: US20240153901A1Publication Date: 2024-05-09
- Inventor: Yu-Hung Lin , Han-Jong Chia , Wei-Ming Wang , Kuo-Chung Yee , Chen Chen , Shih-Peng Tai
- Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
- Applicant Address: TW Hsinchu
- Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee Address: TW Hsinchu
- Main IPC: H01L23/00
- IPC: H01L23/00

Abstract:
A first and second semiconductor device are bonded together using a bonding contact pad embedded within a bonding dielectric layer of the first semiconductor device and at least one bonding via embedded within a bonding dielectric layer of the second semiconductor device. The bonding contact pad extends a first dimension in a first direction perpendicular to the major surface of the first semiconductor device and a second dimension in a second direction parallel to the plane of the first semiconductor wafer, the second dimension being at least twice the first dimension. The bonding via extends a third dimension in the first direction and a fourth dimension in the second direction, the third dimension being at least twice the first dimension. The bonding contact pad and bonding via may be at least partially embedded in respective bonding dielectric layers in respective topmost dielectric layers of respective stacked interconnect layers.
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