Technology is disclosed herein compensating for neighbor memory cell interference on a target memory cell when reading the target memory cell. The voltage that is applied to the bit line associated with the target memory cell may have a magnitude that depends on the data state of the neighbor memory cell. The magnitude of the voltage on the bit line may impact the amount of drain-induced barrier lowering (DIBL) experienced by the target memory cell. The amount of DIBL may be used to provide a desired amount of compensation for the neighbor memory cell interference. A higher bit line voltage may be used to create a greater amount of DIBL and therefore greater amount of compensation for neighbor memory cell interference.