a method of correcting a layout for semiconductor process includes receiving a design layout including a layout pattern for the semiconductor process to form a process pattern of a semiconductor device, where the design layout comprises a pixel-based image associated with the layout pattern and edge information associated with the layout pattern; performing a first layout correction operation on the design layout using a first machine learning model that takes the pixel-based image as input; performing a second layout correction operation on the design layout using a second machine learning model different from the first machine learning model that takes the edge information as input; and obtaining a corrected design layout including a corrected layout pattern corresponding to the layout pattern based on a result of the first layout correction operation and a result of the second layout correction operation.