An integrated circuit device includes a first chip and a second chip. The first chip includes a first substrate including a through-via region, a prohibition region, and a device region, the prohibition region surrounding the through-via region in a plan view. The first chip further includes a through-via penetrating the first substrate in the through-via region, and a power gating cell disposed in the prohibition region. The second chip includes a second substrate, and a plurality of circuit blocks configured to receive power and/or signals through the through-via.