An apparatus includes a plurality of registers; a decoding circuit configured to decode a first instruction; and an execution circuit configured to identify, based on the decoded first instruction, a mode, a first register in which first matrix data is stored, a second register in which second matrix data is stored, and a third register in which third matrix data is stored, select a column of the first matrix data and a row of the second matrix data based on the mode, and perform a multiply accumulate (MAC) operation based on the selected column of the first matrix data, the selected row of the second matrix data, and the third matrix data.