Invention Application
- Patent Title: CUT METAL GATE PROCESS FOR REDUCING TRANSISTOR SPACING
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Application No.: US17588883Application Date: 2022-01-31
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Publication No.: US20220157595A1Publication Date: 2022-05-19
- Inventor: Ming-Chang Wen , Chang-Yun Chang , Hsien-Chin Lin , Hung-Kai Chen
- Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
- Applicant Address: TW Hsinchu
- Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee Address: TW Hsinchu
- Main IPC: H01L21/02
- IPC: H01L21/02 ; H01L21/3215 ; H01L21/3105 ; H01L29/06 ; H01L29/66 ; H01L29/78 ; H01L21/8258 ; H01L21/8238

Abstract:
A semiconductor structure includes a substrate; an isolation structure over the substrate; a first fin extending from the substrate and through the isolation structure; a first source/drain structure over the first fin; a contact etch stop layer over the isolation structure and contacting a first side face of the first source/drain structure; and a first dielectric structure contacting a second side face of the first source/drain structure. The first side face and the second side face are on opposite sides of the first fin in a cross-sectional view cut along a widthwise direction of the first fin. The first dielectric structure extends higher than the first source/drain structure.
Public/Granted literature
- US11721544B2 Cut metal gate process for reducing transistor spacing Public/Granted day:2023-08-08
Information query
IPC分类: