A method of generating an integrated circuit layout diagram includes arranging first cells having a first cell height in a first row and arranging second cells having a second cell height less than the first cell height in a second row abutting the first row. The first row and the second row extend along a first direction and are laid out relative to a routing grid including first routing tracks along the first direction and second routing tracks along a second direction perpendicular to the first direction. First cell pins are placed within each first cell extending along second routing tracks. Second cell pins are placed over selected via placement points in each second cell. At least one second cell pin extends along a corresponding second routing track across a boundary of a corresponding second cell and into a corresponding first cell abutting the corresponding second cell.