- 专利标题: METHOD FOR MANUFACTURING SEMICONDUCTOR WAFER
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申请号: US15772884申请日: 2016-11-08
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公开(公告)号: US20180312992A1公开(公告)日: 2018-11-01
- 发明人: Tadaaki Kaneko , Yasunori Kutsuma , Koji Ashida
- 申请人: KWANSEI GAKUIN EDUCATIONAL FOUNDATION
- 申请人地址: JP Nishinomiya-shi, Hyogo
- 专利权人: KWANSEI GAKUIN EDUCATIONAL FOUNDATION
- 当前专利权人: KWANSEI GAKUIN EDUCATIONAL FOUNDATION
- 当前专利权人地址: JP Nishinomiya-shi, Hyogo
- 优先权: JP2015-220064 20151110
- 国际申请: PCT/JP2016/004832 WO 20161108
- 主分类号: C30B19/04
- IPC分类号: C30B19/04 ; C30B19/12 ; C30B29/36 ; H01L21/02
摘要:
In a first step, protrusions (42) are formed on a surface of an SiC substrate (40), and the SiC substrate (40) is etched. In a second step, the protrusions (42) of the SiC substrate (40) are epitaxially grown through MSE process, and an epitaxial layer (43a) containing threading screw dislocation, which has been largely grown in the vertical (c-axis) direction as a result of MSE process, is at least partially removed. In a third step, MSE process is performed again on the SiC substrate (40) after the second step, to cause epitaxial layers (43) containing no threading screw dislocation to be grown in the horizontal (a-axis) direction to be connected at the molecular level, so that one monocrystalline 4H—SiC semiconductor wafer (45) having a large area is generated throughout an Si-face or a C-face of the SiC substrate (40).
公开/授权文献
- US10508361B2 Method for manufacturing semiconductor wafer 公开/授权日:2019-12-17
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