Invention Application
- Patent Title: METHOD OF FORMING STRAINED MOS TRANSISTORS
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Application No.: US15387712Application Date: 2016-12-22
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Publication No.: US20170194498A1Publication Date: 2017-07-06
- Inventor: Remy Berthelon , Didier Dutartre , Pierre Morin , Francois Andrieu , Elise Baylac
- Applicant: STMicroelectronics (Crolles 2) SAS , STMicroelectronics SA , Commissariat A L'Energie Atomique et aux Energies Alternatives
- Applicant Address: FR Crolles FR Montrouge FR Paris
- Assignee: STMicroelectronics (Crolles 2) SAS,STMicroelectronics SA,Commissariat A L'Energie Atomique et aux Energies Alternatives
- Current Assignee: STMicroelectronics (Crolles 2) SAS,STMicroelectronics SA,Commissariat A L'Energie Atomique et aux Energies Alternatives
- Current Assignee Address: FR Crolles FR Montrouge FR Paris
- Priority: FR1563507 20151231
- Main IPC: H01L29/78
- IPC: H01L29/78 ; H01L21/762 ; H01L29/66 ; H01L21/02

Abstract:
A strained semiconductor layer is produced from a semiconductor layer extending on an insulating layer. A thermal oxidization is performed on the semiconductor layer across its entire thickness to form two bars extending in a direction of a transistor width. Insulating trenches are formed in a direction of a transistor length. A strain of the strained semiconductor layer is induced in one implementation before the thermal oxidation is performed. Alternatively, the strain is induced after the thermal oxidation is performed. The insulating trenches serve to release a component of the strain extending in the direction of transistor width. A component of the strain extending in the direction of transistor length is maintained. The bars and trenches delimit an active area of the transistor include source, drain and channel regions.
Public/Granted literature
- US10263110B2 Method of forming strained MOS transistors Public/Granted day:2019-04-16
Information query
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