A system that includes a PCIe hierarchy may utilize a ring controller for message handling. Nodes acting as the root complex or as endpoint devices may include such ring controllers, portions of which may be implemented by dedicated circuitry on each node. The ring controllers may receive posted transactions representing messages, may return flow control credits for those transactions, may classify each message as to its type, and may write information about each message to a respective ring buffer storing information about messages of that type. A processor (or processing logic/circuitry) on the node may subsequently retrieve messages from the ring buffers and process them. The sizes and locations of the ring buffers in memory may be configurable by software (e.g., by writing to registers within the ring controllers). The message types may include correctable and non-correctable error messages, and non-error messages (including, but not limited to, vendor-defined messages).