Invention Application
- Patent Title: FABRICATION PROCESS FOR MITIGATING EXTERNAL RESISTANCE AND INTERFACE STATE DENSITY IN A MULTIGATE DEVICE
- Patent Title (中): 减少外部电阻和接口状态密度在多设备中的制造工艺
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Application No.: US14197746Application Date: 2014-03-05
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Publication No.: US20150255568A1Publication Date: 2015-09-10
- Inventor: ANIRBAN BASU , Guy Cohen , Amlan Majumdar
- Applicant: International Business Machines Corporation
- Applicant Address: US NY Armonk
- Assignee: International Business Machines Corporation
- Current Assignee: International Business Machines Corporation
- Current Assignee Address: US NY Armonk
- Main IPC: H01L29/66
- IPC: H01L29/66 ; H01L29/205 ; H01L29/78

Abstract:
A method for fabricating a multigate device includes forming a fin on a substrate of the multigate device, the fin being formed of a semiconductor material, growing a first conformal epitaxial layer directly on the fin and substrate, wherein the first conformal epitaxial layer is undoped or lightly doped, growing a second conformal epitaxial layer directly on the first conformal epitaxial layer, wherein the second conformal epitaxial layer is highly doped, selectively removing a portion of the second epitaxial layer to expose a portion of the first conformal epitaxial layer and thereby form a trench, and forming a gate within the trench.
Public/Granted literature
- US09136357B1 Fabrication process for mitigating external resistance and interface state density in a multigate device Public/Granted day:2015-09-15
Information query
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